ANALYSIS, CONFIRMATION AND FPGA IMPLEMENTATION OF VEDIC MULTIPLIER WITH BIST CAPABILITY A thesis survey submitted in the partial completion of the requirement for the award of the degree of Master of Technology in VLSI Style & CAD Submitted by simply Vinay Kumar Roll Number: 60761026 Underneath the Guidance Of Mr. Arun Kumar Chatterjee Lecturer, ECED
Department of Electronics and Communication Executive THAPAR SCHOOL (Formerly Referred to as Thapar Company of Engineering and Technology) PATIALA-147004, INDIA June вЂ“ 2009
I hereby declare which the work which is being provided in the thesis entitled, " Analysis, Confirmation and FPGA Implementation of Vedic Multiplier with BIST CapabilityвЂќ in partial completion of the requirement of the award of amount of M. Tech (VLSI Design & CAD) at gadgets and Communication Department of Thapar University, Patiala, is usually an authentic record of my very own work completed under the direction of Mister. Arun Kumar Chatterjee, Lecturer, ECED. The situation presented through this thesis is not submitted in any other University/Institute for the award of my level.
Vinay Kumar Spin. No . 60761026
It is certified that the above statement created by the student is correct to the most of my knowledge and perception.
Mr. Arun Kumar Chatterjee Lecturer ECED, Thapar University Patiala -147004
Countersigned simply by:
Dr . A. K. Chatterjee Professor & Head Electronics and Connection Engg. Section Thapar University or college, Patiala - 147004
Doctor R. K. Sharma Leader Academic Affairs Thapar School Patiala вЂ“ 147004
To find, analyze and to present something totally new is to opportunity on an untrod unbeaten path towards and unexplored destination is an arduous experience unless a single gets an absolute torchbearer to show the way. I might have never prevailed in doing my activity without the assistance, encouragement that help provided in my experience by various people. Words are often also less to reveals oneвЂџs deep regards. I take this opportunity to share my outstanding sense of gratitude and respect for all those who helped me through the life long this thesis. I recognize with honor and humility my indebtedness to Mister. Arun Kumar Chatterjee, Lecturer, ECED, Thapar University, Patiala, under in whose guidance I had fashioned the privilege to finish this thesis. I wish to exhibit my profound gratitude towards her for providing specific guidance and support through the entire thesis work. I communicate my genuine thanks to Doctor A. K. Chatterjee, Professor & Mind of Gadgets & Connection Department, Thapar University, Patiala for his encouragement and cooperation. My spouse and i express my personal heartfelt gratitude towards Mrs. Alpana Agarwal, Assistant Mentor & PG coordinator, ECED, Thapar College or university, Patiala, because of their valuable advice, encouragement, ideas and the eagerness with which the girl solved my personal difficulties in VLSI Design & CAD Lab. I might also like to thank most staff members and my co-students who were ever present at the will need of the hour and supplied with all the help and services, which I necessary for the completing my thesis. My very best thanks should be all who also wished me personally success especially my parents. Especially I render my honor to the Luminous who bequeathed self-confidence, ability and durability in me personally to total this be employed by not permitting me down at the time of problems and showing me the silver lining in the dark clouds.
Vinay Kumar ii
This thesis work is definitely devoted for that layout of a high-speed Vedic multiplier, its rendering on reconfigurable hardware and Built in Do it yourself Testing (BIST) of the applied multiplier. Interfacing of FPGA with a PS2 KEYBOARD is done. To get arithmetic multiplication various Vedic multiplication techniques like Urdhva tiryakbhyam, Nikhilam and Anurupye has been thoroughly discussed. It has been found that Urdhva tiryakbhyam Sutra is quite efficient Sutra (Algorithm), giving minimum postpone for copie of all types of amounts, either little...
Himanshu Thapliyal and Meters. B Srinivas, " An effective Method of Elliptic Curve Encryption Using Historic Indian Vedic MathematicsвЂќ, IEEE, 2005.
" Spartan-3E FPGA Starter Package Board User GuideвЂќ, UG230 (v1. 1) June 20, 2008